/* ========================================================================== */
/*                                                                            */
/*   Filename.c                                                               */
/*   (c) 2001 Author                                                          */
/*                                                                            */
/*   Description                                                              */
/*                                                                            */
/* ========================================================================== */
#include "boardtest.h"


HY57V283220_SDRAM_init()
{
    EMIFA_Config emifaCfg0 = {
        EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)      |
        EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, SDRAM64)      |
        EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(7))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(1)),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, SYNC32)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
        
        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
        
        EMIFA_FMKS(SDEXT, WR2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(3))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(2))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(2))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(6))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),            
        EMIFA_CESEC_DEFAULT,
        EMIFA_CESEC_DEFAULT,
        EMIFA_CESEC_DEFAULT,
        EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2)    |
        EMIFA_FMKS(CESEC, RENEN, READ)         |
        EMIFA_FMKS(CESEC, CEEXT, ACTIVE)       |
        EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)      |
        EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
    };
	/* Initialize EMIFA */
    EMIFA_config(&emifaCfg0);
}


/*
 *  Memory functions
 */
 
Int16 MEM_fill(Uint32 start, Uint32 len, Uint32 val)
{
    Uint32 i, end;
    
    /* Calculate end of range */
    end = start + len;
    
    /* Fill a range with a value */
    for (i = start; i < end; i+=4)
    {
        *((Uint32 *)i) = val;
    }
        
    /* Verify the data */
    for (i = start; i < end; i+=4)
    {
        if (*((Uint32 *)i) != val)
            return 1;
    }
    
    return 0;
}

Int16 MEM_addr(Uint32 start, Uint32 len)
{
    Uint32 i, end;
    
    /* Calculate end of range */
    end = start + len;
    
    /* Fill the range with its address */
    for (i = start; i < end; i+=4)
    {
        *((Uint32 *)i) = i;
    }

    /* Verify the data */
    for (i = start; i < end; i+=4)
        if (*((Uint32 *)i) != i)
            return 2;
    
    return 0;
}

Int16 MEM_addrInv(Uint32 start, Uint32 len)
{
    Uint32 i, end;
    
    /* Calculate end of range */
    end = start + len;
    
    /* Fill the range with its address */
    for (i = start; i < end; i+=4)
    {
        *((Uint32 *)i) = ~i;
    }

    /* Verify the data */
    for (i = start; i < end; i+=4)
        if (*((Uint32 *)i) != (~i))
            return 4;
    
    return 0;
}

Int16 MEM_walking(Uint32 add)
{
    Int16 i;
    Uint32 mask, *pdata;
    
    pdata = (Uint32 *)add;

    /* Walking ones and zeros */
    mask = 1;
    for (i = 0; i < 32; i++)
    {
        /* Test one in bit position i */
        *pdata = mask;
        
        /* Do a dummy write to Flash to clear bus */
        *((Uint8 *)EVMDM642_FLASH_BASE) = 0xf0;
        
        /* Check data */
        if (*pdata != mask)
            return 1;
            
        /* Test zero in bit position i */
        *pdata = ~mask;
        
        /* Do a dummy write to Flash to clear bus */
        *((Uint8 *)EVMDM642_FLASH_BASE) = 0xf0;

        /* Check data */
        if (*pdata != (~mask))
            return 8;
            
        mask = mask << 1;
    }
    
    return 0;
}

Int16 MEM_bytestrobe(Uint32 add)
{
    Uint32 *pdata;
    Uint8 *pcheck;
    
    /* Write pattern */
    pdata = (Uint32 *)add;
    *pdata = 0x12345678;
    
    /* Do dummy write */
    pdata = (Uint32 *)EVMDM642_FLASH_BASE;
    *pdata = 0x80808080;
    
    /* Check pattern */
    pcheck = (Uint8 *)add;
    if (*pcheck++ != 0x78)
        return 0x10;
    if (*pcheck++ != 0x56)
        return 0x20;
    if (*pcheck++ != 0x34)
        return 0x40;
    if (*pcheck++ != 0x12)
        return 0x80;
        
    return 0;
}

Int16 MEM_test(Uint32 start, Uint32 len, Int16 patterntype)
{
    Int16 status = 0;
    
    if (!patterntype)
    {
        /* Run the fill tests */
        status |= MEM_fill(start, len, 0x00000000);
        status |= MEM_fill(start, len, 0x77777777);
        status |= MEM_fill(start, len, 0x88888888);
        status |= MEM_fill(start, len, 0xFFFFFFFF);
    } else
    {
        /* Run the address tests */
        status |= MEM_addr(start, len);
        status |= MEM_addrInv(start, len);
    }
        
    return status;
}

/*
 *  POST tests
 */

Int16 TEST_intMem()
{
    Int16 status = 0;
    
    /* Check internal memory (byte 0x20000 to byte 0x40000) */
    status |= MEM_test(0x20000, 0x20000, 0);
    status |= MEM_test(0x20000, 0x20000, 1);
    status |= MEM_walking(0x20000);
      
    return status;
}
#define SDRAM1_BASE 0x80000000
#define SDRAM2_BASE 0x81000000
Int16 TEST_extMem()
{
    Int16 status = 0;
	Int32 local_counter = 0;
	Uint8  check = 0;
    
    /* Check external memory (byte 0x80000000 to byte 0x82000000) */
//    status |= MEM_test(0x80000000, 0x02000000, 0);
//    status |= MEM_test(0x80000000, 0x02000000, 1);
//    status |= MEM_walking(0x80000000);
//    status |= MEM_bytestrobe(0x80000000);

	for( local_counter = 0; local_counter < 0x100; local_counter++)
	{
		*((Uint8 *)(SDRAM2_BASE + local_counter)) = local_counter;
	}

	for( local_counter = 0; local_counter < 0x100; local_counter++)
	{
		check = *((Uint8 *)(SDRAM2_BASE + local_counter));
		if(check != (local_counter)){
			status = 1;
		}
	}  

	
	for( local_counter = 0; local_counter < 0x1000; local_counter++)
	{
		*((Uint8 *)(SDRAM2_BASE + local_counter)) = 0x55;
	}

	for( local_counter = 0; local_counter < 0x1000; local_counter++)
	{
		check = *((Uint8 *)(SDRAM2_BASE + local_counter));
		if(check != (0x55)){
			status = 1;
		}
	}  
  
  
	for( local_counter = 0; local_counter < 0x1000; local_counter++)
	{
		*((Uint8 *)(SDRAM2_BASE + local_counter)) = 0xaa;
	}

	for( local_counter = 0; local_counter < 0x1000; local_counter++)
	{
		check = *((Uint8 *)(SDRAM2_BASE + local_counter));
		if(check != (0xaa)){
			status = 1;
		}
	}           
    return status;
}

//End of File

